資工趴趴熊的小天地

莫爾模型

輸出值則僅是目前狀態的函數 ， 因為正反器的輸出與時脈同步)

使用JK正反器的莫爾模型

使用JK正反器的莫爾模型 --design   bench

module Moore_Model_Fig_5_19 (
  output [1: 0] y_out, 
  input	x_in, clock, reset
);
  reg [1: 0]	state;
  parameter	S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;//將每一個部分輸入好

  always @ (posedge clock, negedge reset)
    if (reset == 0) state <= S0;	// 若reset=0時，將S0輸給state
    else case (state) // 若reset=1時，根據x_in是1或0輸入 S
      S0:	if (~x_in) 	state <= S1; else state <= S0;
      S1: if (x_in) 	  	state <= S2; else state <= S3;
      S2:	if (~x_in) 	state <= S3; else state <= S2;
      S3: if (~x_in)   	state <= S0; else state <= S3;
    endcase 

  assign y_out = state;	// 最後的y_out輸出看state
 
endmodule 

---

使用JK正反器的莫爾模型 --test   bench

module t_Moore_Fig_5_19;
  wire [1: 0]	t_y_out; 
  reg		t_x_in, t_clock, t_reset;

Moore_Model_Fig_5_19 M0 (t_y_out, t_x_in, t_clock, t_reset);

initial #200 $finish;
initial begin t_clock = 0; forever #5 t_clock = ~t_clock; end

initial fork
       t_reset = 0;
  #2 t_reset = 1;
  #87 t_reset = 0;
  #89 t_reset = 1;
  #10 t_x_in = 1;
  #30 t_x_in = 0;
  #40 t_x_in = 1;
  #50 t_x_in = 0;
  #52 t_x_in = 1;
  #54 t_x_in = 0;
  #70 t_x_in = 1;
  #80 t_x_in = 1;
  #70 t_x_in = 0;
  #90 t_x_in = 1;
  #100 t_x_in = 0;
  #120 t_x_in = 1;
  #160 t_x_in = 0;
  #170 t_x_in = 1;
  
  join
endmodule

---

使用T型正反器的莫爾模型

使用T型正反器的莫爾模型 --design   bench

module Moore_Model_Fig_5_20 (
  output	y_out, 
  input	x_in, clock, reset
);
  reg [1: 0]	state;
  parameter	S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;

  always @ (posedge clock, negedge reset)
    if (reset == 0) state <= S0;	// 若reset為0，輸入S0給state
    else case (state)  // 若reset為1時，看case決定輸入哪一個
      S0:	if (x_in) 	state <= S1; else state <= S0;
      S1: if (x_in) 	state <= S2; else state <= S1;
      S2:	if (x_in) 	state <= S3; else state <= S2;
      S3: if (x_in)   	state <= S0; else state <= S3;
    endcase 

  assign y_out = (state == S3);	// y_out輸出
endmodule 

module Toggle_flip_flop_3 (Q, T, Clk, rst);
  output 	Q;
  input	T, Clk, rst;
  reg 	Q;

  always @ (posedge Clk, negedge rst)	
    if (!rst) Q <= 1'b0;
    else  Q <= Q ^ T;	 
endmodule

module Moore_Model_STR_Fig_5_20 ( //這裡是主要內容
  output	y_out, A, B, 
  input	x_in, clock, reset
);
  wire	TA, TB;

// Flip-flop input equations
  assign TA = x_in & B;
  assign TB = x_in;
//output equation
  assign y_out = A & B;
// Instantiate Toggle flip-flops
  Toggle_flip_flop_3 M_A (A, TA, clock, reset);
  Toggle_flip_flop_3 M_B (B, TB, clock, reset);

endmodule 

---

使用T型正反器的莫爾模型 --test  bench

module t_Moore_Fig_5_20;
  wire 	t_y_out_2, t_y_out_1; 
  reg	t_x_in, t_clock, t_reset;

  Moore_Model_Fig_5_20 M1(t_y_out_1, t_x_in, t_clock, t_reset);
  Moore_Model_STR_Fig_5_20 M2 (t_y_out_2, A, B, t_x_in, t_clock, t_reset);


  initial #200 $finish;
  initial begin
         t_reset = 0;
         t_clock = 0;
    #5 t_reset = 1;
    repeat (16)
      #5 t_clock = ~t_clock;
  end
  initial begin
           t_x_in = 0;
    #15 t_x_in = 1;
    repeat (8)
      #10 t_x_in = ~t_x_in;
  end
endmodule