資工趴趴熊的小天地

JK正反器

輸入方程式

                   

 

JK型正反器--design   bench

module JK_flip_flop_1 (Q, Q_not, J, K, Clk, RST_B);  //描述JK線路圖
  output 	Q, Q_not;
  input	J, K, Clk, RST_B;
  wire	JK;
  assign	JK = (J & ~Q) | (~K & Q);
  assign	Q_not = ~Q; 
  D_flip_flop_AR M0 (Q, JK, Clk, RST_B);  //JK正反器中間有一塊D型(可rst的)
 endmodule

module JK_flip_flop_2 (Q, Q_not, J, K, Clk);  //描述JK性質
  output 	Q, Q_not;
  input	J, K, Clk;
  reg 	Q;
  assign	Q_not = ~Q;
  always @ (posedge Clk)	
    case ({J, K})
      2'b00:	Q <= Q;
      2'b01:	Q <= 1'b0;
      2'b10:	Q <= 1'b1;
      2'b11:	Q <= ~Q;
    endcase
 endmodule

---

JK型正反器--test   bench

module t_JK_flip_flop;  
  wire 	Q, Q_not;
  reg	J, K, Clk, RST_B;

  JK_flip_flop_1  M1 (Q_1, Q_1_not, J, K, Clk, RST_B);  //描述JK線路圖
  JK_flip_flop_2  M2 (Q_2, Q_2_not, J, K, Clk);  //描述JK性質

 
  initial #100 $finish;
  initial begin Clk = 0; forever #5 Clk = ~Clk; end
  initial fork
    RST_B = 0;
    RST_B = 1;
    J = 0;
    K = 0;
    #20 K = 1;
    #40 J = 1;
    #80 K = 0;
    #90 J = 0;
   join
endmodule